1. Field of the Invention
The present invention generally relates to the applications of space-charge-limited conduction (SCLC) induced current increase in nitride-oxide dielectric capacitors. One major application of the invention is with a voltage regulator and more particularly to a nitride-oxide dielectric capacitor voltage regulator. This invention is also applicable to other applications such as DRAM process controls (node dielectric thickness, defect, film uniformity, etc.), voltage sensors, space-charge-limited dielectric amplifiers, and SCLC memory devices.
2. Description of the Related Art
Voltage regulators are important components in power supply circuits and are used to maintain constant output voltage regardless of minor variations in load current or input voltage. For example, commonly used voltage regulators range from simple Zener regulators to relatively complicated voltage-regulating circuits. Tremendous amounts of waste power and relatively high temperature sensitivity make simple two-terminal Zener diode regulators impractical for on-chip power supply circuits.
Integrated voltage-regulating circuits can achieve much better power performance than Zener diodes; however, they employ many devices such as MOSFETs, capacitors, diodes, and resistors. Thus, they are structurally more complicated and physically consume larger die space than simple diodes or capacitor regulators. Although voltage regulators could be implemented off-chip or on-package to save die space, this implementation is not as effective and easy to use as on-chip very large scale integrated circuits (VLSIs).
The continued scaling down of DRAM cell sizes requires a thinner, higher quality, and more reliable storage node dielectric to compensate for decreased surface area and to reduce defect density. Recent trends have shown that the nitride-oxide stacked dielectric thin film becomes an attractive choice for the storage capacitor of large DRAM chips. However, the individual thickness of each layer (nitride and oxide) and the information about the traps inside this material system are hard to measure and control. Conventionally, a capacitance-voltage (C-V) method is used to obtain the electrical thickness and trap concentration for the device. However, C-V measurements can only measure the total thickness (the effective thickness) of the stack. C-V data analysis is difficult due to impacts from quantum-mechanical effects, gate leakage current, and series resistance effects caused by aggressive scaling of the dielectric thickness. Furthermore, the C-V method alone cannot determine the energy level of the traps. TEM is another method conventionally used to determine physical thickness of stacked structure. However, it is destructive, costly, localized, and tedious. It cannot be used for determining uniformity across the wafer or used as a routine in-line monitor.
The invention provides a nitride-oxide stacked structure that produces an abrupt current increase at the voltage VTFL (trap filled limit voltage) prior to dielectric breakdown. Both planar and deep trench type devices could be fabricated by using this structure. Two things happen when the VTFL is reached, first, the capacitor current increases drastically. Secondly, the applied voltage across the capacitor remains relatively constant over a wide range of device current values. Numerous applications, such as voltage regulator, voltage sensor, DRAM/eDRAM process control, and SCLC memory device, find benefit with this inventive structure.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a structure which has a nitride layer, a reoxidized nitride (re-oxide) layer on a nitride layer, and input and output connections. There are carrier traps inside the nitride layer and at the interface between the nitride and re-oxide layer. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a constant voltage is output for a plurality of currents. The trap filled limit voltage events can occur at different current levels, such that the invention produces a multi-value voltage regulator in one embodiment.
The power consumption of the invention""s two-terminal N-O capacitor based voltage regulator is much less than Zener diodes based voltage regulator since it is operated below the dielectric breakdown voltage. The leakage current tunneling through amorphous N-O film is much less than the leakage current traveling through Si after breakdown of a Zener diode.
The present invention""s N-O trench type voltage regulator has extremely high density (deep trench approach) design and is the best choice for space saving. On-chip voltage regulation with mass integration becomes possible by using the deep trench N-O capacitor as a inventive voltage regulator. This approach is also easily integrated and has low cost.
The invention is also useful with dynamic random access memory (DRAM) process control. Details of SCLC conduction parameters depend on the thickness and temperature. VTFL voltages are shown below to be proportional to the square of the film thickness. Since the re-oxide thickness is kept constant for all of the films, the variation of VTFL depends on nitride thickness only. There is no electrical method conventionally available to detect nitride thickness and re-oxide thickness separately for N-O stacked film. However, the invention provides such an electrical test methodology by combining VTFL I-V result and normal C-V result. The electrical thickness of the individual layer is thereby easily determined. Furthermore, nitride consumption rate during re-oxidation is also obtained with the invention. The activation energy extracted from temperature dependent SCLC current shows the characteristics of the traps. Therefore, the SCLC conduction parameters are easily monitored and are used to control the thickness and the level of defects during DRAM fabrication.